Partially Depleted Silicon on Insulator Phase Lock Loop

Abstract

A 435-MHz, Digital Low-IF (1-MHz), Double Differential Phase Shift Keying (DDPSK) Transceiver circuit for space application was the motivation for engineering our low power Quadurature Phase Lock Loop (PLL). The PLL was designed to meet specifications set forth by NASA and JPL. In this thesis, you will gain knowledge of the implemented design, transistor sizes, the layout as a whole, and the calculations used for the system design. The design consists of two cross-coupled NMOS and PMOS pair analog Voltage Controlled Oscillators with a digital feed back loop.