A Feasibility Study on the application of Stream Architectures for Packet Processing Applications

Abstract

A new breed of processors has emerged for packet processing applications, called Network Processors (NP). These processors make use of co-processors, which are dedicated hardware, to perform key computational kernels at wire speed. This reduces the flexibility of the Network Processor. This thesis looks into the inefficiencies of the current architecture employed and the feasibility a stream architecture for packet processing applications. The thesis simulates the performance of an IPv4 forwarding algorithm on a generic stream architecture and characterizes the maximum sustainable throughput of the forwarding engine. The algorithm has been implemented with

maximizing performance being the focus. The architecture has been tweaked to accommodate the algorithm. The forwarding engine developed is able to sustain a data rate of OC-48 running on a 500 MHz clock. It also incorporates a bit extraction engine which makes it flexible to support different routing schemes.