Modeling Layout Dependent Stress Effects for CMOS.

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dc.contributor.advisorWilliam Davis, Chairen_US
dc.contributor.advisorPaul Franzon, Memberen_US
dc.contributor.advisorMehmet Ozturk, Memberen_US
dc.contributor.advisorNaihuan Jing, Memberen_US
dc.contributor.authorDemircioglu, Harunen_US
dc.date.accepted2013-11-04en_US
dc.date.accessioned2013-11-06T10:30:12Z
dc.date.available2013-11-06T10:30:12Z
dc.date.defense2013-09-30en_US
dc.date.issued2013-09-30en_US
dc.date.released2013-11-06en_US
dc.date.reviewed2013-10-28en_US
dc.date.submitted2013-10-24en_US
dc.degree.disciplineElectrical Engineeringen_US
dc.degree.leveldissertationen_US
dc.degree.nameDoctor of Philosophyen_US
dc.identifier.otherdeg3011en_US
dc.identifier.urihttp://www.lib.ncsu.edu/resolver/1840.16/8989
dc.rightsen_US
dc.titleModeling Layout Dependent Stress Effects for CMOS.en_US

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