Active Body Bias for Low-Power Silicon-On-Insulator Design
| dc.contributor.advisor | W. Rhett Davis, Committee Member | en_US |
| dc.contributor.advisor | Antonio Montalvo, Committee Member | en_US |
| dc.contributor.advisor | Brian Hughes, Committee Member | en_US |
| dc.contributor.advisor | Paul Franzon, Committee Chair | en_US |
| dc.contributor.advisor | Angus Kingon, Committee Member | en_US |
| dc.contributor.author | Damiano, John | en_US |
| dc.date.accessioned | 2010-04-02T18:41:41Z | |
| dc.date.available | 2010-04-02T18:41:41Z | |
| dc.date.issued | 2007-04-18 | en_US |
| dc.degree.discipline | Electrical Engineering | en_US |
| dc.degree.level | dissertation | en_US |
| dc.degree.name | PhD | en_US |
| dc.description | North Carolina State University Theses Electrical and Computer Engineering.;North Carolina State University Theses Electrical and Computer Engineering. | |
| dc.description.abstract | SOI device technology offers the circuit designer higher performance and greater flexibility. This work proposes the use of a targeted substrate bias and innovative device and circuit topologies to achieve higher performance and lower power while providing a strategy to compensate for wide temperature and process variations. This project introduces and evaluates a modified H-gate device topology (integrated drain-body transistor, or IDBT) vs. alternative structures using simulation supported by electrical results obtained from test circuits. The IDBT can be used to locally and dynamically reduce MOSFET VTH, increase switching speed, and improve circuit energy-delay product by up to 30%. For all structures investigated, the dynamic body bias provided by IDBTs provides improved logic cell performance vs. conventional source-tied cell designs. This work also examines use of body bias to compensate for temperature or process variations. The temperature range seen by space electronics exceeds standard commercial specs and even military specs. Integrated circuits placed on a satellite or lander vehicle may be expected to operate from below -200°C to over 200°C. In this environment, the stabilization of key circuit parameters across temperature, whether power consumption or performance metrics, can be accomplished through a targeted substrate bias. The amount of stabilization available, i.e. the degree to which key parameters can be shifted in-situ, is explored. Similarly, variations in device parameters due to process variations can also be compensated using this technique. Finally, these efforts exposed marginalities in the models for Honeywell MOI5 MOSFETs. At low temperatures, the simulated device characteristics diverged substantially from the electrical data, while the PMOS device simulation results displayed incorrect body factor. This work interprets these results and develops improved models based on electrical results from a series of test structures. | en_US |
| dc.format | Thesis (Ph.D.)--North Carolina State University. | |
| dc.identifier.other | etd-03312006-003214 | en_US |
| dc.identifier.uri | http://www.lib.ncsu.edu/resolver/1840.16/3990 | |
| dc.rights | I hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to NC State University or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report. | en_US |
| dc.subject | SOI | en_US |
| dc.subject | circuit design | en_US |
| dc.subject | silicon-on-insulator | en_US |
| dc.subject | body bias | en_US |
| dc.subject | layout techniques | en_US |
| dc.subject | layout | en_US |
| dc.title | Active Body Bias for Low-Power Silicon-On-Insulator Design | en_US |
| dcterms.abstract | Keywords: SOI, circuit design, silicon-on-insulator, body bias, layout techniques, layout. | |
| dcterms.extent | xii, 131 pages : illustrations (some color) |
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