A Testbed for Technology Characterization

Abstract

As feature sizes continue to decrease, fundamental properties of MOSFET devices begin to hinder the performance gains from one generation to another. The advent of the Tunneling Field Effect Transistor (TFET) provides hope for continued reduction in feature size whilst solving some of the scaling issues such as leakage current. The purpose of this work is to discuss key metrics that help to quantify the improvements among technology nodes, specifically a comparison between TFETs and traditional MOSFETs. Test structures that allow for the measurement of on and off current, device speed, variation as it relates to on current and threshold voltage, as well as SRAM yield and bitcell read and write noise margins are discussed. In addition, a slight modification to a rapid characterization test structure used to measure threshold variation is proven to help reduce leakage seen within the test structure. Lastly, the structures are actually fabricated in a 90nm bulk and a 45nm SOI process and measurements from the 90nm bulk process are presented.