Design and Power Optimization of a 16 nm Dual Floating Gate FET Memory Array and Peripheral Circuits.

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dc.contributor.advisorPaul Franzon, Chairen_US
dc.contributor.advisorBrian Floyd, Memberen_US
dc.contributor.advisorGregory Byrd, Memberen_US
dc.contributor.authorBhattacharyya, Abhisheken_US
dc.date.accepted2013-12-03en_US
dc.date.accessioned2013-12-04T10:30:12Z
dc.date.available2013-12-04T10:30:12Z
dc.date.defense2013-08-05en_US
dc.date.issued2013-08-05en_US
dc.date.released2013-12-04en_US
dc.date.reviewed2013-08-07en_US
dc.date.submitted2013-08-06en_US
dc.degree.disciplineComputer Engineeringen_US
dc.degree.levelthesisen_US
dc.degree.nameMaster of Scienceen_US
dc.identifier.otherdeg2865en_US
dc.identifier.urihttp://www.lib.ncsu.edu/resolver/1840.16/9115
dc.rightsen_US
dc.titleDesign and Power Optimization of a 16 nm Dual Floating Gate FET Memory Array and Peripheral Circuits.en_US

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