A Data-Parallel, Hardware-Accelerated Monte Carlo Framework for Quantifying Risk using Probabilistic Circuits.

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dc.contributor.advisorMihai Diaconeasa, Chair
dc.contributor.advisorYousry Azmy, Member
dc.contributor.advisorNam Dinh, Member
dc.contributor.advisorAydin Aysu, Member
dc.contributor.authorEarthperson, Arjun
dc.date.accepted2025-11-18
dc.date.accessioned2025-11-20T13:30:40Z
dc.date.available2025-11-20T13:30:40Z
dc.date.defense2025-08-04
dc.date.issued2025-08-04
dc.date.released2025-11-20
dc.date.reviewed2025-08-08
dc.date.submitted2025-08-04
dc.degree.disciplineNuclear Engineering
dc.degree.leveldissertation
dc.degree.nameDoctor of Philosophy
dc.identifier.otherdeg43332
dc.identifier.urihttps://www.lib.ncsu.edu/resolver/1840.20/46261
dc.titleA Data-Parallel, Hardware-Accelerated Monte Carlo Framework for Quantifying Risk using Probabilistic Circuits.

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