Verilog Design and Verification of an Application Specific Branch Predictor for astar Benchmark.

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dc.contributor.advisorEric Rotenberg, Chair
dc.contributor.advisorJames Tuck, Member
dc.contributor.advisorHuiyang Zhou, Member
dc.contributor.authorVastrad, Adith Sagar
dc.date.accepted2019-07-08
dc.date.accessioned2020-07-09T12:31:03Z
dc.date.available2020-07-09T12:31:03Z
dc.date.defense2019-05-08
dc.date.embargo2020-07-09
dc.date.issued2019-05-08
dc.date.released2020-07-09
dc.date.reviewed2019-05-09
dc.date.submitted2019-05-08
dc.degree.disciplineComputer Engineering
dc.degree.levelthesis
dc.degree.nameMaster of Science
dc.identifier.otherdeg16556
dc.identifier.urihttps://www.lib.ncsu.edu/resolver/1840.20/38089
dc.titleVerilog Design and Verification of an Application Specific Branch Predictor for astar Benchmark.

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