Parallel Logic Level Simulation of VLSI Circuits

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dc.contributor.authorBagrodia, R.
dc.contributor.authorLi, Z.
dc.contributor.authorJha, V.
dc.contributor.authorChen, Y.
dc.contributor.authorCong, J.
dc.date.accessioned2012-01-12T18:50:27Z
dc.date.available2012-01-12T18:50:27Z
dc.date.issued1994
dc.format.extent1058529 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://www.lib.ncsu.edu/resolver/1840.4/6602
dc.language.isoen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.relation.ispartofseriesWinter Simulation Conference Proceedings
dc.titleParallel Logic Level Simulation of VLSI Circuits
dc.typeTechnical report

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