Design of a Self-test Vehicle for AC Coupled Interconnect Technology

dc.contributor.advisorDr. W. Rhett Davis, Committee Memberen_US
dc.contributor.advisorDr. Paul Franzon, Committee Memberen_US
dc.contributor.advisorDr. John Wilson, Committee Chairen_US
dc.contributor.authorShah, Manav Rajendraen_US
dc.date.accessioned2010-04-02T17:58:07Z
dc.date.available2010-04-02T17:58:07Z
dc.date.issued2006-04-24en_US
dc.degree.disciplineElectrical Engineeringen_US
dc.degree.levelthesisen_US
dc.degree.nameMSen_US
dc.description.abstractThe recent need for higher data rates has lead to the deployment of high density multi-gigabit interconnect technologies. AC coupling is one such technology which has been demonstrated to achieve high signaling speeds. With I/O interconnect speeds growing rapidly, engineers have to find efficient ways of designing hardware circuits to characterize and test these high speed interfaces. The quality of any interconnect technology, including its transceivers, can be analyzed by its BER (Bit Error Rate) performance. Traditionally, BER is evaluated using software simulations and stand-alone BER test products, which are either time-consuming orexpensive. We have developed a versatile BER testing system which exhibits advantages in speed and cost over existing solutions. In this thesis, we demonstrate the design and implementation of a self-contained FPGA-based system to test the AC coupled interconnects. We present a user-configurable system that is capable of generating and evaluating the ITU-T recommended test patterns simultaneously over three channels with data rates of up to 3 Gb/s per channel. The high speed BER logic is developed in verilog, while C-based drivers are written for an on-chip PowerPC processor to handle slow book-keeping tasks. An RS232 interface, which allows the user to remotely configure the system and obtain the BER results, is provided. The complete system is implemented and tested on an FPGA development board. The test system is evaluated on the basis of factors such as maximum operating speed, jitter specifications for the transceiver and intrinsic BER. Special recommendations for successful design of an 8-layer PCB (Printed Circuit Board) and the optimum selection of components are discussed. A complete schematic design of the ACCI test system is presented. This system will be used as a self-test vehicle on a low-orbit satellite to perform testing of AC coupled interconnects (including transceivers) and gather BER results. This thesis also serves as a base for developing complex test structures for high-speed interconnect protocols such as Infiniband, XAUI, PCI Express, Gigabit Ethernet, Fiber Channel etc. It should provide an interesting discussion for people trying to build test systems based on hardware/software co-design.en_US
dc.identifier.otheretd-04212006-010425en_US
dc.identifier.urihttp://www.lib.ncsu.edu/resolver/1840.16/748
dc.rightsI hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to NC State University or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report.en_US
dc.subjectACCIen_US
dc.subjectBERen_US
dc.subjectSelf-Test Systemen_US
dc.titleDesign of a Self-test Vehicle for AC Coupled Interconnect Technologyen_US

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