The Effectiveness of Global Difference Value Prediction And Memory Bus Priority Schemes for Speculative Prefetch

Abstract

Processor clock speeds have drastically increased in the recent years. However, the cycle time improvement in the DRAM semiconductor technology used for memories has been comparatively slow. The expanding processor — memory gap encourages developers to find aggressive techniques to reduce the latency of memory accesses.

Value prediction is a powerful approach to break true data dependencies. Prefetching is another technique, which aims to reduce the processor stall time by bringing data into the cache before it is accessed by the processor. Recovery-free value prediction [26] scheme combines these two techniques and uses value prediction only for prefetching so that the need for validation of predictions and a recovery mechanism for mispredictions are eliminated.

In this thesis, the effectiveness of using global difference value prediction for recovery-free speculative execution is studied. A bus model is added for modeling the buses in the memory system. Three bus priority schemes, First Come First Served (FCFS), Real Access First Served (RAFS) and Prefetch Access First Served (PAFS), are proposed and their performance potentials are evaluated when a stride and a hybrid global difference predictor (hgDiff) is used. The results show that the recovery-free speculative execution using value prediction is a promising technique that increases the performance significantly (up to 10%), and this increase depends on the bus priority scheme and the predictor used.