Hardware Implementation of an XML Parser

Abstract

EXtensible Markup Language (XML) is fast emerging as the most preferred language for data exchanges between heterogeneous web servers and databases. This in turn has propelled the deployment and use of "XML-aware" networking equipment like routers, switches and appliances. With network speeds touching tens of Gbps, the heavily CPU-intensive, software-based XML processing methods fail to deliver the required throughput, posing a severe bottleneck to network performance. The need for exploring alternative solutions for parsing and validating XML data has thus assumed prime importance today. The thesis presents an efficient hardware implementation of an XML parser, which ensures that the incoming XML is "well-formed" and "valid". This involves checking of the document for syntactical correctness and verifying it against the corresponding XML Schema for validity. The system delivers a peak throughput of 1.2Gbps.