STI Friendly Clock Recovery Techniques for Bit Banged Communication Protocols

Abstract

Nowadays embedded communication networks are used in a number of applications. A majority of these networks use a shared medium for communication. Controllers for these shared medium protocols can be implemented in hardware or software. Protocol implementations in software using standard off the shelf microcontrollers have been found to be faster, easier and most cost effective.

In an embedded communication network, it is essential that the protocol controllers are in synchrony with each other. A slight phase difference between the clocks of the protocol controllers can lead to errors in the data propagated between them. If the sender has a slight error in its clock frequency the receivers that are reading a message from the sender need to adapt to the clock of the sender by recovering the clock information from the data on the shared medium. This paper talks about the various existing techniques in hardware and software and compares a few proposed clock recovery techniques which can be used for software protocol implementations using STI.

A good clock recovery technique must adapt to the sender as quickly as possible and maintain very little phase difference with the sender. It must consume very few computational cycles and the code blocks must remain as close together as possible to avoid fragmenting the idle time of the protocol implementation.

In order to facilitate STI, a good primary thread implementation will need to have large chunks of idle time which can be merged with useful code from a secondary thread. It is also required that the primary thread should have fixed or almost fixed execution times for all its functions, in order to be able to recover as much idle time as possible.

The proposed techniques have large chunks of idle time as well as try to catch up with the sender's clock as quickly as possible. Hence they are good candidates for being used in software protocol implementations using STI. However, the limitation of these techniques is the fixed number of cycles up to which they can recover in every bit interval when the receiver's clock is slower than the sender's.