Methods of fabricating single electron transistors in which the thickness of an insulating layer defines spacing between electrodes
| dc.date.accessioned | 2008-07-23T15:26:54Z | |
| dc.date.available | 2008-07-23T15:26:54Z | |
| dc.date.issued | 2004 | |
| dc.format.extent | 81441 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.citation | Brousseau, L. C., III. (2004). Methods of fabricating single electron transistors in which the thickness of an insulating layer defines spacing between electrodes. U.S. Patent No. 6,784,082. Washington, DC: U.S. Patent and Trademark Office. | |
| dc.identifier.uri | http://www.lib.ncsu.edu/resolver/1840.2/921 | |
| dc.language.iso | en | |
| dc.title | Methods of fabricating single electron transistors in which the thickness of an insulating layer defines spacing between electrodes | |
| dc.type | Patent |
