Structure and method to fabricate self-aligned transistors with dual work function metal gate electrodes

Simple item page
dc.date.accessioned2008-10-13T21:37:52Z
dc.date.available2008-10-13T21:37:52Z
dc.date.issued2006
dc.format.extent130607 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.citationChambers, J. J. (2006). Structure and method to fabricate self-aligned transistors with dual work function metal gate electrodes. U.S. Patent No. 7,005,365. Washington, DC: U.S. Patent and Trademark Office.
dc.identifier.urihttp://www.lib.ncsu.edu/resolver/1840.2/1328
dc.language.isoen
dc.titleStructure and method to fabricate self-aligned transistors with dual work function metal gate electrodes
dc.typePatent

Files

Original bundle

Now showing 1 - 1 of 1
No Thumbnail Available
Name:
US_7005365_B2_I.pdf
Size:
127.55 KB
Format:
Adobe Portable Document Format
Download

License bundle

Now showing 1 - 1 of 1
No Thumbnail Available
Name:
license.txt
Size:
1.76 KB
Format:
Plain Text
Description:
Download

Collections

Publications