Advanced Gate Stacks for Strained Si Devices

Abstract

Due to the mobility enhancement provided by strained Si for both electrons and holes, as well as the scaling requirement and potential issues of polysilicon gate electrodes, alternative gate stacks are being pursued for strained Si devices, which warrant investigation for better understanding on the integration of high-K dielectrics and metal gate electrodes. Mobility enhancement of strained Si devices has been reported even with ultra-thin SiO2. However, additional scattering mechanisms related with high-K dielectrics and strained Si may result in mobility degradation, which requires a fundamental study. Furthermore, impacts of integration of metal gate electrodes with strained Si channels are not fully understood.

In this work, an investigation of the degradation of electrical properties of several candidate metal gate electrodes on high k dielectrics on strained Si was performed and compared with that of bulk Si samples. This work consists of three parts. Strained Si layers were grown on relaxed SiGe virtual substrates by ultrahigh vacuum rapid thermal chemical vapor deposition (UHV/RTCVD). High-K dielectrics and metal gates were formed by physical vapor deposition (PVD) methods. The first part of the study focused on the optimization of experimental conditions and the investigation of results from material analysis. The second part of this study compared electrical data from MOS capacitors fabricated with metal gate electrodes on strained Si with SiO2 as the gate dielectric with that of HfO2. Different strained Si thickness and different Ge concentration in the virtual substrate were employed to study the effects of strain and Ge out-diffusion on electrical properties. Results from strained Si MOSFETs on SiO2 or HfO2 with TaN gate electrodes achieved by standard and advanced electrical characterization, including mobility measurement, two and three level charge pumping methods, were analyzed in the last part. It was found that electrical properties degraded as the strained silicon thickness decreased, which was attributed to the presence of Ge in the strained Si layer, and more degradation was observed with SiO2 which may be due to Si consumption during oxidation. This trend of increasing degradation with decreasing strained silicon thickness did not change after rapid thermal annealing. Metal gate electrodes were found to exhibit as good performance on strained Si as on bulk Si. Strain does not lead to any degradation of the high-K/strained Si interface. Ge diffusion is the dominant cause of the Dit increase, which explains that thinner strained Si samples show less device performance enhancement. Less degradation with HfO2 samples was observed due to the low temperature formation process of high-K dielectrics. The mechanisms responsible for mobility degradation in strained Si devices with advanced gate stacks were discussed.