Growth, Characterization and Device Processing of GaN Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Structures

Abstract

The physical properties of GaN, high saturation velocity, high breakdown fields, high electron mobility, wide bandgap energy and high thermal conductivity, make it a promising material for field effect transistor (FETs) devices for high speed, high power, and small channel length applications. Despite the success of GaN electronic devices such as heterojunction field effect transistors (HFETs), fabrication of GaN Metal Oxide Semiconductor (MOS) transistors remains a technical challenge. The primary reason for this is the non-availability of a gate dielectric with a low density of interface states and the simultaneous requirement of ohmic source/drain contacts which are compatible with enhancement mode structures. Unlike existing III-N HFET devices, which have a high free carrier density two dimensional electron gas (2DEG) in the semiconductor substrate, a MOSFET in either accumulation or inversion mode requires low free carrier concentration in the semiconductor channel, and a high density of free carriers in adjacent source and drain areas. This research explores the development, and demonstration of an enhancement mode (normally off) GaN MOSFET with highly doped source/drain ohmic contacts and compatible gate dielectric.

Highly doped source/drain ohmic contacts were formed by selected area epitaxial regrowth of Si doped GaN by metalorganic chemical vapor deposition (MOCVD). The MOS gate dielectrics which have been investigated are Ga2O3/Gd2O3 and SiNx. To achieve uniform and highly doped GaN on reactive ion etched (RIE) and patterned GaN surfaces for source drain contacts, a low temperature regrowth (750-850oC) was developed. A model for growth morphology consistent with the low temperature regrowth of GaN on RIE patterned GaN surfaces is given. The detailed structural, optical, and chemical characterization of the low temperature regrown highly doped GaN for source and drain contacts has been provided. The structural characterization of GaN/Ga2O3/Gd2O3 interface used in MOS device fabrication is presented. Devices were fabricated based on III-N structures and epitaxial MOS dielectrics. The GaN MOSFET structures fabricated in this work exhibited enhancement mode (normally off) operation. This proof of concept demonstration of normally off GaN MOSFETs with epitaxially regrown source and drain contacts is a significant step in the development of enhancement mode III-N MOSFET devices for logic, high speed, high power and high temperature applications.