Providing Static Timing Anlaysis Support for an ARM7 Processor Platform

Abstract

Scratchpad memory provides faster speed but smaller capacity than other memories do in embedded systems. It provides a visibly heterogeneous memory hierarchy rather than abstracting it as cache memory does. Unlike cache memory, program code and data can be allocated into the scratchpad memory as desired. This enables optimizing the performance in real-time embedded systems. Static timing analysis helps the optimization processes by providing microscopic information of the application program's timing information. Based on the WCET and BCET estimated by static timing analysis, the techniques using scratchpad memory may be enhanced.

This study aims to provide a method of static timing analysis for an ARM processor platform (ARM7TDMI). Basic analysis is performed relying on well-known program analysis graphs such as control flow graphs, call graphs, depth-first search trees, and post-dominance trees. During this basic analysis, loops and unstructured code are also identified, which make static timing analysis more difficult. A control dependence analysis is a convenient way to analyze the WCET and BCET, since it represents the hierarchical control structure of a program. By traversal of the control dependence graph, the WCET and BCET are estimated.

To confirm the feasibility of this study, a real target system and its development environment tool chains are developed and an existing application is ported. In addition, the static timing analysis framework of this study is implemented by the tool named ARMSAT. Experiments are performed in these all environments. The experimental results show that the actual execution times are bounded by the calculated analytical WCET and BCET bounds, although there are a few factors which interfere with computing the analytical execution times.