Printed circuit patterned embedded capacitance layer

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dc.date.accessioned2008-10-17T18:19:50Z
dc.date.available2008-10-17T18:19:50Z
dc.date.issued2006
dc.format.extent137783 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.citationDunn, G. J., Croswell, R. T., Magera, J. A., Savic, J. & Tungare, A. V. (2006). Printed circuit patterned embedded capacitance layer. U.S. Patent No. 7,138,068. Washington, DC: U.S. Patent and Trademark Office.
dc.identifier.urihttp://www.lib.ncsu.edu/resolver/1840.2/1736
dc.language.isoen
dc.titlePrinted circuit patterned embedded capacitance layer
dc.typePatent

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