Power-Scalable Memory: Exploiting Typical Charge Retention in DRAM and Charge-Voltage Decoupling in ZettaRAM

Abstract

DRAM faces two fundamental power scaling challenges in the future. Firstly, DRAM requires continuous refresh because of charge leakage, resulting in power consumption even during standby operation. As DRAM capacity quadruples with each new generation, standby power grows correspondingly and becomes a significant fraction of system power. Secondly, we are fast approaching a lower limit on DRAM voltage scaling because charge in a DRAM capacitor depends directly on voltage, and a minimum amount of charge is needed for reliable operation.

Scalable standby power is achieved by exploiting typical charge leakage instead of worst-case charge leakage. Most DRAM cells have very low leakage currents and consequently long retention times. However, sparse outliers have high leakage currents and short retention times, and are the cause for frequent refreshes of the whole DRAM. More generally, retention times of DRAM cells and even whole pages vary widely, with an average retention time on the order of seconds. We propose Retention-Aware Placement in DRAM (RAPID), novel software techniques that can exploit off-the-shelf DRAMs to reduce refresh power to vanishingly small levels. The key idea is to favor allocation of longer-retention pages over shorter-retention pages, and then select a single refresh period that depends on the shortest-retention page among populated pages instead of the shortest-retention page overall. This refresh period is much higher than the default refresh period of commodity DRAMs, thereby significantly reducing the frequency of refreshes. Thus, RAPID reduces DRAM standby power to near-zero levels, yielding favorable standby power scaling despite quadrupling of DRAM capacity from one generation to the next.

To overcome DRAM voltage scaling limits, we explore the long-term power-scalability of ZettaRAM™, a nascent DRAM technology. ZettaRAM is based on conventional DRAM architectures but replaces the DRAM capacitor with a new molecular capacitor. The molecular capacitor is fully charged⁄discharged if the applied voltage is above⁄below a discrete threshold voltage. Therefore, unlike a conventional capacitor, the amount of charge deposited on the molecular capacitor is independent of applied voltage. Charge-voltage decoupling holds the key for viable voltage scaling from one generation to the next and opens up two unprecedented power scaling opportunities.

(1) Exploiting molecular engineering for long term power scalability: Read⁄write operations can be performed at lower voltages, while still maintaining the minimum amount of charge needed for reliable sensing. Precise tuning of molecular attributes provides an inexpensive path for scaling voltage, hence power, from one memory generation to the next, whereas conventional DRAM requires major cell redesigns to maintain a fixed charge while scaling voltage.

(2) Intelligent management of ZettaRAM: While the fixed charge is voltage-independent, speed is voltage dependent. Thus, the applied voltage is padded to achieve the same speed as DRAM. A key architectural insight is leveraged to manage the speed-voltage dependence and lower the voltage even further: most of the bitline activity is caused by non-critical L2-cache writeback requests. Accordingly, slow operations (lower voltage) are applied to non-critical writebacks and fast operations (higher voltage) to critical fetches. This hybrid policy combines the power efficiency of uniformly slow operations with the high performance of uniformly fast operations, further extending ZettaRAM's power scaling advantage.

The combination of RAPID and ZettaRAM leads to a power-scalable form of DRAM, extending the roadmap of this important memory technology.