Slipstream mode Prefetching in CMP's: Performance Comparison and Evaluation

Abstract

With the increasing gap between processor speeds and memory, many programs with large working sets do not derive significant benefits from caching. As a result, many architects have turned to prefetch mechanisms. Prefetching works by predicting data items that will be referenced by application programs in the future and fetching them into the cache a priori to reduce cache misses. The slipstream mode of execution was recently proposed for multiprocessors built from dual-processor CMP's, as a means to improve performance of parallel programs that have reached their scalability limits. The prediction of future loads, in this case, is based on actual execution, rather than history-based prediction in conventional hardware prefetchers.

The contribution of this thesis is to evaluate the performance of prefetching while running an application in slipstream mode and comparing it with performance obtained from conventional hardware prefetchers. The objective of this work is to find out whether the use of an available extra processor for the purposes of prefetching to reduce coherence misses, is justified.

We find that slipstream mode provides 10-13% additional speedup, compared to a good hardware prefetcher, for two of the four applications we studied. We also observe that prefetching in slipstream mode has a higher accuracy than other prefetchers. Due to this, we believe that slipstream mode will continue to perform well with an increasing number of CMP's.