Tradeoffs Involved in Design of SRAMs

Abstract

This thesis explores the tradeoffs that are involved in the design of SRAMs. The major components of an SRAM such as the row decoders, the memory cells and the sense amplifiers have been studied in detail. The circuit techniques used to reduce the power dissipation and delay of these components have been explored and the tradeoffs have been explained.

The key to low power operation in the SRAM data path is to reduce the signal swings on the high capacitance nodes like the bitlines and the data lines. A unique resetting scheme for the row decoders has been proposed. Using this technique the word line pulse width can be minimized and the signal swings on the bitlines is reduced.

Finally a 4Kb prototype SRAM has been designed and verified. This design incorporates some of the circuit techniques used to reduce power dissipation and delay. Experimental data has been provided which shows the effectiveness of using the resetting scheme for the row decoders. The design was simulated at a clock speed of 500Mhz. The read access time was found to be 0.83ns while the write access time was found to be 0.62ns. The total power dissipation was 26.3mW.