Packet Processing on Stream Architecture

Abstract

Stream processing architectures have been proposed as efficient and flexible platforms for network packet processing. This is because packet processing shares many of the same characteristics of media and image processing that motivate stream architectures: little global data reuse, abundant data parallelism, and high computational complexity. This dissertation explores the SIMD (Single Instruction, Multiple Data) stream architecture for network packet processing with several security-related applications. The implementations are based on the stream programming model on the Imagine media processor, which consists of three tiers of memory hierarchy and eight VLIW clusters operating in SIMD mode.

The applications explored are listed as follows: the Advanced Encryption Standard (AES)in parallel operation modes with key agility, theMultilinear Modular Hash (MMH) message authentication code, Bloom-filter-based content inspection engine for signature-based intrusion detection, and the sketch update for Internet traffic analysis. Some novel methodologies are also presented as applications being transformed and implemented on the stream architecture.

The thesis characterizes the processing throughput of these applications and explores the tradeoffs on different configurations of stream architecture. Moreover, the sketch update application is also implemented on the Intel IXP network processor, in order to explore the difference between Imagine and a traditional architecture. The SIMD operation simplifies the access to shared data structure without explicit synchronization and arbitration overhead. As a result, the system achieves efficient utilization of maximum memory bandwidth.

The architecture demonstrates the flexibility to support computation-intensive packet processing tasks at high performance. Applications such as hash and statistical based tasks are best fit into the stream programming model with an abundance of producer and consumer locality: portions of values computed and stored in the stream register file (SRF) are used for calculating a new set of values recursively. With a 500-MHz clock, the stream processor is capable of processing packets up to multi-gigabit-per-second throughput with outstanding power efficiency.

Although packet processing over the SIMD stream architecture exhibits control flow and load balancing issues due to packet size variation, the analysis indicates that the multi-core, multi-SIMD architecture improves the performance and efficiency. Further explorations are proposed as promising directions for future research.