FPGA Implementation of a SIP Message Processor

Abstract

Session Initiation Protocol (SIP) is fast emerging as the next generation signaling protocol. It operates independently of the underlying network transport protocol, establishing sessions between multiple users irrespective if the media is voice, data or video. It is projected to eventually replace the existing multiple voice and video signaling protocols as a single protocol which achieves all. SIP implements a non-trivial grammar. Parsing this grammar to extract the protocol fields proves to be a high overhead for the CPU. This paper presents hardware offload architecture; the SIP Offload Engine (SOE) which essentially extracts the SIP fields and stores them is a proprietary data structure, for easy access by the CPU. An analysis has been done which shows a reduction in the CPU overhead by as much as 90%.