Flexible ASIC Design using the Block Data Flow Paradigm (BDFP)

Abstract

An Application Specific Integrated Circuit (ASIC) outperforms most processors; however, it is limited to one algorithm. Instruction Level Parallelism (ILP) processors, which include mixed type processors such as the Digital Signal Processor (DSP), the Very Long Instruction Word (VLIW) Processor, the Reduced Instruction Set Computer (RISC), and the Complex Instruction Set Computer (CISC), are popular due to their flexibility and programmability. Thus, they can be used for many different applications. However, their cost-performance can not meet the needs of many real world applications.

In this research, we mapped three different algorithms, the one-dimensional Finite Impulse Response (1D-FIR), the two-dimensional Finite Impulse Response (2D-FIR), and the two-dimensional Infinite Impulse Response (2D-IIR) filter into the same flexible hardware architecture using the Block Data Flow Paradigm (BDFP). The idea of a Flexible Application Specific Integrated Circuit (FASIC) is to design a mixed architecture using an ASIC for the fixed part of the system while using a Field Programmable Gate Array (FPGA) for the part of the system that requires a change of parameters for different algorithms. The Block Data Flow Parallel Architecture (BDPA) design, which has near super computer performance for media processing, is meant to form part of the FASIC library (Intellectual Property, IP) and is to be integrated with a general purpose host computer or mixed processor computer as an accelerator.

The FASIC, designed in this research, not only can accommodate different algorithms but also can flexibly change its configuration to obtain different cost-performance and frequency response outputs according to each system specification. We used the block data overlap-save algorithm for implementing the FIR filter system. This allows linear speedup performance if proper data input/output (I/O) and block size are given. We used the state space concept to implement the 2D-IIR filter system, which also has the characteristic of linear speedup to a saturation point. In order to solve the data flow bottleneck problem which exists in most multiprocessor systems, we have designed a hierarchical data flow control architecture, an input data distributor, and a data source regulator. These designs are flexible and asynchronously controllable so that they can easily accommodate different algorithms. We used a one dimensional array architecture to reduce wafer area, pin connections, and power consumption (compared to a 2D array architecture). We used a four processor module array in the 2D-FIR filter system, which was designed on a multiprocessor system using a clock with two different frequencies. This system has throughput performance of 7.975 samples per processor clock cycle and the processor utilization is 78.53%.