High level timing specification of instruction-level parallel processors

dc.contributor.authorHarcourt, Ed
dc.contributor.authorMauney, Jon
dc.contributor.authorCook, Todd
dc.date.accessioned2007-01-04T19:55:13Z
dc.date.available2007-01-04T19:55:13Z
dc.date.issued1993
dc.format.extent380604 bytes
dc.format.extent399636 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/postscript
dc.identifier.uriftp://ftp.ncsu.edu/pub/unity/lockers/ftp/csc_anon/tech/93/TR-93-18.ps.Z
dc.identifier.urihttp://www.lib.ncsu.edu/resolver/1840.4/758
dc.language.isoen
dc.publisherNorth Carolina State University. Dept. of Computer Science
dc.relation.ispartofseriesTR-93-18
dc.relation.ispartofseriesDepartment of Computer Science Technical Report
dc.titleHigh level timing specification of instruction-level parallel processors
dc.typeTechnical report

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