FabIssue: Automatic RTL Generation of Issue Logic in Superscalar Processors for Core Customization.

dc.contributor.advisorEric Rotenberg, Committee Chairen_US
dc.contributor.advisorHuiyang Zhou, Committee Memberen_US
dc.contributor.advisorJames Tuck, Committee Memberen_US
dc.contributor.authorMayukh, Hiranen_US
dc.date.accepted2010-08-06en_US
dc.date.accessioned2010-08-07T07:00:15Z
dc.date.available2010-08-07T07:00:15Z
dc.date.defense2010-06-16en_US
dc.date.issued2010-06-16en_US
dc.date.released2010-08-07en_US
dc.date.reviewed2010-07-06en_US
dc.date.submitted2010-07-05en_US
dc.degree.disciplineComputer Engineeringen_US
dc.degree.levelthesisen_US
dc.degree.nameMaster of Scienceen_US
dc.identifier.otherdeg161en_US
dc.identifier.urihttp://www.lib.ncsu.edu/resolver/1840.16/6117
dc.rightsI hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to NC State University or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report.en_US
dc.titleFabIssue: Automatic RTL Generation of Issue Logic in Superscalar Processors for Core Customization.en_US

Files

Original bundle

Now showing 1 - 1 of 1
No Thumbnail Available
Name:
etd.pdf
Size:
1008.46 KB
Format:
Adobe Portable Document Format

Collections