Integrated circuit having reduced probability of wire-bond failure

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dc.date.accessioned2008-10-16T16:05:49Z
dc.date.available2008-10-16T16:05:49Z
dc.date.issued2000
dc.format.extent109898 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.citationKermani, B. G. (2000). Integrated circuit having reduced probability of wire-bond failure. U.S. Patent No. 6,153,506. Washington, DC: U.S. Patent and Trademark Office.
dc.identifier.urihttp://www.lib.ncsu.edu/resolver/1840.2/1643
dc.language.isoen
dc.titleIntegrated circuit having reduced probability of wire-bond failure
dc.typePatent

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